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SpyGlass CDC is the industry's most comprehensive, practical, and powerful CDC verification product

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SemiWiki Blog: A Comprehensive Solution for Addressing CDC Issues
The SpyGlass® Constraints solution provides a productivity boost to IC design efforts by automating the creation, validation and management of constraints

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Expert Constraint Management Leads to Productivity & Faster Convergence
BugScope™ is a full-chip assertion synthesis product that automatically generates assertions and functional coverage properties for progressive and targeted verification of complex designs

Methodology for Assertion Reuse in SoC Designs

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SpyGlass Power provides the only complete solution for power optimization at RTL

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View the SpyGlass Power Webinar
SpyGlass Advanced Lint analyzes an RTL design using formal techniques without requiring user supplied assertions or test vectors

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The SpyGlass DFT solution
is the only tool that comprehensively enables early test closure at RTL

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GenSys RTL integrates easily into any existing design flow and provides powerful RTL modification tools that avoid manual errors, endless scripting and rework

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Atrenta's IP Kit, built on the industry-standard SpyGlass platform, comprises a set of checks specifically targeted to handoff third-party IP blocks or internally developed designs

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当社の業務

AtrentaのSpyGlass Predictive Analyzer® は、世界の主要な半導体メーカーや民生機器メーカーのデザイン効率 を、大いに改善しています。こうしたなか、この特許ソリューションは今日のコンシューマエレクトロニクス製品の複雑なSoCに要求されるパフォーマンス、パワーやエリアに対して、設計初期段階での解析を可能にします。世界中で200を超える企業および何千人ものデザインエンジニアが従来のEDAツールを用いて設計する前にリスクとコストを減少させるためSpyGlassを用いて解析しています。そしてさらに、BugScope™によって検証効率も強化され、エンジニアや管理者が、複雑なSoCのシリコンへの最も速く、最もコストのかからないパスを見つけることを可能にしています。

SpyGlass from Atrenta: Insight. Efficiency. Confidence.

ニュース

Aug 21, 2014
Looking For The Next Big Thing
Published by: SemiEngineering  
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Aug 07, 2014
IP/SoC Verification With Assertions
Published by: SemiEngineering  
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Aug 07, 2014
Test Becomes Power-Aware
Published by: SemiEngineering  
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Aug 07, 2014
When Will 2.5D Cut Costs?
Published by: SemiEngineering  
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Aug 07, 2014
Established Nodes Getting New Attention
Published by: SemiEngineering  
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Aug 04, 2014
Designing For Security
Published by: SemiEngineering  
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Jul 31, 2014
Making IP Reuse and SoC Integration Easier
Published by: SemiWiki  
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Jul 31, 2014
IP And FinFETs At Advanced Nodes (Part 3)
Published by: SemiEngineering  
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