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Newsletter

- Analytics-June 2010 - Atrenta Announces SpyGlass-Physical; ST Cites Success, Atrenta Hosts 3-D SoC Design Flow Demo, Power Analysis of Clock Gating at RTL, Experts at the Table: Nice to Have Vs. Need to Have, Atrenta's SpyGlass®-CDC Solution Reduces Design Risk for Fujitsu Microelectronics Europe, Wicked Rumor Video - Atrenta at DAC, SpyGlass-Power Tips & Tricks, Free White Paper: Power Analysis of Clock Gating at RTL,Workshop on SpyGlass®-Power, Webcast: High IP Quality Seminar By Atrenta and Denali and more...

- Analytics-April 2010 - Incorporating Quality into Reusable IP, Stacked Dies Gain Attention, But So Far Little Traction, Exploring the Types of Combinational Loops, SoC Designers Must Have Tangible Quality Metrics for Semiconductor Intellectual Property, Increasing the Level of Abstraction of IC Design, How 238 Users See "Primary EDA Vendor" Pitch, Rob Roy Joins Atrenta Executive Team,Atrenta/Denali/Springsoft Buy Everyone's DAC Passes This Year!, Free Whitepaper on Verification of Multi-Clock Designs and more...

- Analytics-February 2010 - Arasan Joins Atrenta's SpyLinks™ Partner Program, STARC Collaborates with Atrenta on EDA Tool Quality Management System, STARC Adopts Atrenta SpyGlass®-Power for RTL Power Estimation and Verification, Atrenta SpyGlass® Solutions for Early Testability and Low Power Design Adopted by NEC Electronics, Sign-off Metrics for IP Quality - EDACafe Video, White Paper on Low Power Design, Workshop on SpyGlass®-Power and more...

- Analytics-December 2009 - Atrenta SpyGlass®-Constraints SDC Equivalence Verification Capability Adopted by STARC, Atrenta's SpyGlass®-CDC Solution Boosts IP Integration Efficiency for Fujitsu Kyushu Network Technologies, A Register Transfer Level Approach to Memory Built-in Self Test and Repair Insertion, White Paper: Facilitating At-speed Test at RTL, Workshop: SpyGlass®-DFT - Design for Test, Webinar: Early Design Closure with SpyGlass, Atrenta-Denali Joint Seminar - High Quality Semiconductor IP, Atrenta at EDSF and more...

- Analytics-October 2009 - Experts at the Table: What's Next, Considerations for Choosing the Right Low-Power Tools, Atrenta Inc Receives 2009 Best of San Jose Award , Free White Paper : Verification of Multi-Clock Design, Workshop on SpyGlass®-CDC, Atrenta SpyGlass 4.3.0 Release, Atrenta SpyGlass 4.3.0 Webinar and more...

- Analytics-September 2009 - Message from Mike Gianfagna, Experts at the Table: What's Next, Semiconductor Design and Manufacture Predictability, Atrenta Event Update, Atrenta Product Update, Free White Paper : Approach and Techniques for Power Estimation, Reduction and Verification, Workshop On SpyGlass® Power and more

- Analytics-August 2009 - Message from Mike Gianfagna , Verification and Generation of Constraints, Changing SoC Design Methodologies to Automate IP Integration and Reuse, RTL Approach Supports Memory BIST and Repair Insertion, White Paper: Approach and Techniques for Preserving the Intent of Timing Constraints Throughout the Design Flow, Workshop on SpyGlass-Constraints and more...

- Analytics-April 2009 - Design Quality Enhances Company Survival, Experts at the Table: Platform-Based Design, Performance or Time to Market. What's Your Choice?, Streamlining IP-based Chip Design, Hear about Atrenta???s efforts to improve IP quality, Mike Gianfagna Speaks at DesignCon 2009, SpyGlass® Workshop, Free White Paper: SpyGlass® Application in an FPGA to ASIC Conversion and more...

- Analytics-March 2009 - New Atrenta Support Portal, Announcing SpyGlass 4.2.0 Release, Boosting SoC Design Productivity for the iPhone Generation, Recrafting the Concept of EDA, Chip Design in Recession: A View from an ASIC Consolidator, DS2 Adopts Atrenta SpyGlass® for Advanced ASIC Design, Free White Paper: Automated Assembly and IP Integration Techniques for SoCs and more..

- Analytics-February 2009 - Mike Fazeli Joins Atrenta, Tieto Joins Atrenta's SpyLinks™ Partner Program, Atrenta's SpyGlass®-CDC Solution Boosts IP Integration Efficiency for Atheros, Atrenta Seminars in India a Huge Success, Power Opto and Linting in CatapultC and SpyGlass®, Atrenta Recognized as Top 5 EDA Vendor by Siliconindia, Atrenta CEO Delivered Keynote Address at the 22nd Intl. Conference on VLSI Design and more...

 
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