How to Achieve Power Estimation, Reduction and Verification in Low Power Design

Power dissipation is a major concern in modern day IC design. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and can be an effective differentiator. Mobile phones, PDAs, digital cameras and personal MP3 players are increasingly being sold on the long battery lives...

Power Analysis of Clock Gating at RTL

This White Paper discusses a solution for clock gating analysis and implementation at RTL for power reduction. The RTL approach is important because designers usually verify power only at the gate level and any change to the RTL needs many design iterations to reduce power. The RTL solution thus saves weeks of effort by fixing potential power issues up-front.

SoC Physical Closure Begins at RTL!

Any survey of chip design teams consistently points to two problem areas impacting quality and schedule of today’s SoCs. Those areas are: a) completeness of verification, and b) physical design closure for area, timing and power for complex IP’s and SoC’s. With the advent of deep sub-micron technology, these problem areas have become exacerbated. In this White Paper, we take a closer look at the physical design closure aspects of advanced SoCs. We provide a root cause analysis of unpredictable physical design closure issues and explore possible solutions and methodologies to address these problems

Designing for Test at RTL

Design for test (DFT) techniques impose rigorous and generally well-known constraints on a design. These constraints include issues with respect to clock generation and distribution, asynchronous sets and resets, memory controls and tristate busses...

RTL Fault Coverage Estimation

This paper describes a method for estimating fault coverage from register transfer level (RTL) descriptions of complex circuits. The method does not require automatic test pattern generation (ATPG) or the use of fault simulation and therefore offers the advantage of very rapid turnaround with no additional user effort. An important benefit is the means for a user to quickly determine the change in fault coverage while considering various changes to a design. The technique automatically takes advantage of available designed in test logic and may be applied to either combinational or sequential test generation tools.

Facilitating At-speed Test at RTL

This white paper demonstrates a solution for facilitating at-speed test at the register-transfer level. The RTL approach is important, because designers and test engineers usually verify the test coverage only at the gate level during the final ATPG stage. This RTL solution thus saves weeks of effort by fixing potential issues up front.

A Register Transfer Level Approach to Memory Built-in Self Test and Repair Insertion

This white paper describes a novel approach for memory built-in self test (MBIST) and repair insertion at the register transfer level (RTL). The approach is independent of BIST IP technology and works with any supplier's qualified ASIC design kit and BIST libraries. The methodology describes both a bottom up and a top down approach to SoC design and validation - all at the RTL stage. Application of this approach on real industrial designs indicates enhancement of design productivity and shorter cycle time for functional validation.

Do your Chip a Favor! Manage the Constraints!!

Design goes through several transformations in a typical RTL-to-layout flow. There are several verification steps in place to make sure that the design intent has not changed. For example, simulation, equivalence checking and so on. In practice, Timing Constraints are created at RTL level just as RTL is created and are refined throughout the design cycle...

Constraints Management: Approach and Techniques for Preserving the Intent of Timing Constraints throughout the Design Flow

Constraints management is a major concern for designers today and increasing design complexity, coupled with mounting time to market pressure, makes faster timing closure and reduced iterations a necessity. Any late stage constraint change brings with it enormous costs, both in terms of time and money, and can lead to a failed design project.

Verification of Multi-Clock Designs

This white paper outlines a holistic approach to resolving issues associated with ever increasing numbers of clock interfaces, where data is transferred between clocks of different frequencies and often between asynchronous domains. The paper suggests exercising various technologies as part of an intuitive user environment, and highlights why addressing one issue in isolation can at best jeopardize timing closure, and at worst introduce silicon risk.

Combining Structural and Functional Verification Techniques to Improve Effective CDC Verification

Multiple, independent clocks have become a fact of life on SoCs and other complex ASICs. In extreme cases, such as in large communications processors, clock domains may number in the thousands. Clock domain crossings pose a growing challenge to chip designers...

SpyGlass Application in an FPGA to ASIC Conversion

Mapping an FPGA design to an ASIC can be a problem-free experience if the FPGA was designed from the outset with a re-map in mind. If you did not take this precaution, you may find that so many changes are required to make the FPGA RTL ASIC-compliant that you must effectively re-design and re-verify the RTL. In this case, the FPGA implementation becomes little more than an existence proof that a working implementation can be built. By following the Atrenta GuideWare? methodology using the SpyGlass? family of tools, you can achieve portability of the design from the FPGA implementation to the ASIC implementation, and from one process node to the next. Atrenta?s GuideWare methodologies contain a comprehensive set of checks and qualified templates that allow for maximal portability of the design.

GuideWare™

Advances in silicon technology have enabled unprecedented levels of integration in today's SoC designs. This white paper describes typical issues faced by designers in a typical work-flow for today's SoC designs that includes new block/subsystem RTL development, IP selection and SoC level integration. The paper highlights the need to address implementation issues for the chip project early in the design cycle. The paper then reviews current "rule-checking" approaches and gives an overview of the Atrenta approach to the problem.

Automated Assembly and IP Integration Techniques for SoCs

Platform-based methodology is projected to become the dominant approach for SoC design in the very near future. Automated assembly techniques equally will become the standard approach for building these designs in order to manage complexity, time to market and development cost. Adopting such techniques can have significant impact on each of these factors and carries a significantly lower startup cost than many people assume. More importantly, these techniques are starting to become a competitive advantage, especially in consumer segments. In this White Paper, we have reviewed the key steps needed to implement automated assembly methods. We have reviewed the costs and benefits associated with these tasks and discussed how they are working today for real designs.