Early Implementation Feasibility Analysis for RTL Blocks

IP leads and SoC integrators need to make decisions that impact the power, timing and physical feasibility of a chip during the downstream implementation flow. As they have limited visibility into physical implementation and the SoC context in which the design will get integrated to, the impact of these decisions are resolved late in the process. The result can be several iterations between back-end and front-end designers, a costly problem.

The SpyGlass?? Physical Advanced solution evaluates multiple floorplan configurations, analyzes implementation feasibility, enables appropriate IP selection, creates physical partitions and generates implementation guidance for IP and SoC implementation. With the SpyGlass Physical solution, IP leads and SoC integrators can make sure IP RTL will be easier to implement and will meet SoC design goals.

Key Features

• Enables critical area, power, timing and congestion trade-offs early in the design phase
• Provides rich visualization, interactivity and reporting to determine physical feasibility
• Provides quick and accurate what-if analysis of architecture and micro-architecture both at IP and SoC levels
• Provides accurate and fast what-if analysis of multiple floorplan configurations
• Generates floorplan and constraints guidance for IP and SoC development
• Provides partitioning of physical blocks to meet SoC targets quickly
• Provides support for connectivity abstractions such as interface definitions and transaction specifications
• Provides fast analysis to enable multiple iterations within a day

Key Benefits

• Provides fast analysis to enable multiple iterations within a day leading to faster design closure
• Enables IP leads and SoC designers to take corrective action based on analysis without having to learn deep physical concepts
• Provides a rich set of visualization, what-if analysis, reports and metrics enabling easy to use floorplanning for complex IP and SoCs
• Makes existing flows more efficient and significantly reduces overall design closure time